Conventional non-volatile memory (NVM) cells typically include a gate oxide formed over a substrate. The thickness and quality of the gate oxide can have tremendous influence on NVM retention (the ability of the NVM cell to retain data). In general, a thicker or higher quality gate oxide can lead to better NVM retention. However, with the size reduction of NVM cells in complementary metal oxide semiconductor (CMOS) processes, the gate oxide of the NVM cells has become thinner and thinner.
One approach to overcoming this problem involves using a dual gate oxide (DGO) process, where two layers of gate oxide are formed. For example, a 1.8V gate oxide may be deposited on top of a 3.3V gate oxide. However, not all manufacturing platforms can provide multiple gate oxide thicknesses. Also, in some circumstances, adding multiple oxide layers together still cannot provide adequate gate oxide thickness.
Another approach involves growing oxides having different thicknesses in a single oxidation step (where the NVM gate oxide is thicker). This often involves preparing a silicon surface with nitrogen implantation before an oxidation process. However, the gate oxide quality from this process is typically not good, which allows higher leakage current and degrades NVM retention. It also requires the use of an extra nitrogen implant process step.